In semiconductor technology, various integrated circuit features (such as doped regions and gate stacks) are formed on a substrate by various processes including photolithography process, ion implantation, etching and deposition. An interconnection structure (including various conductive features, such as contact features, via features and metal lines) is formed and configured to connect integrated circuit features into a functional circuit. For example, damascene processes may be utilized to form multilayer copper interconnections. However, the existing methods cause various issues, such as parasitic capacitance and bridging (leakage), which undesirably impacts the circuit performance, such as introducing additional time delay or cause the circuit malfunction. Especially, when the semiconductor technologies move forward to advanced technology nodes with smaller feature sizes, such as 20 nm, 16 nm or less, the parasitic capacitance issue is further deteriorated, which further leads to degradation of the circuit performance and reliability.
Therefore, the present disclosure provides an interconnection structure and a method making the same to address the above issues.